Hardware Accelerator

This talk from the Storage Networking Industry Association (SNIA) discusses the growth in data-centric tasks in data centers today. These consist of multiple streams of high bandwidth data for storage, networking or security applications. This trend has created the need for new hardware such as smart NICs, DPUs (data processing units) and other xPUs which contain accelerators to offload tasks from the main CPU. At Azimuth Technology, our first IP offering is a hardware accelerator for cryptography which can be integrated into the coherent domain of a CPU, GPU or DPU to accelerate TLS encryption/decryption.

Our current IP in development is a hardware accelerator (HWA) to accelerate cryptographic processing targeted towards RISC-V or ARM cores. Hardware accelerators allow computing systems to accelerate the performance of a particular class of applications by providing hardware support at the algorithmic level.

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We attended the Open Domain-Specific Architecture (ODSA) workshop on \”Prototyping Chiplet Based Open Data Accelerators\” at the end of August 2021. ODSA is part of the Open Compute Project (OCP). The chiplet approach to building a systems-in-package (SiP) consists of integrating silicon die from one or more vendors onto a common package. The band of wires (BoW) standard allows two chipsets to communicate using one or more protocols such as CHI, AXI4(5) as well as point-to-point wires using a set of low latency high-speed links. The benefit of the chiplet approach is it allows vendors to build their own hardware accelerator in silicon to optimize targeted applications using the BoW for off-chip communication.

An emerging paradigm presented at the workshop was computational storage and the corresponding system architecture changes to move computation closer to storage. Instead of copying data from I/O to main memory, then decrypting or uncompressing it, followed by copying back to user memory, an accelerator in a storage SiP can eliminate one or more data copies. It could also support a bump in the fabric model allowing processing to occur as data is read from I/O by the accelerator en route to a CPU or GPU.

Hi everyone – hope you and your families are enjoying the summer! Here is a status update on our progress.

RTL development of the closely coupled version of the cryptographic hardware accelerator (HWA) has commenced on Amazon Web Services (AWS).

The RTL is being coded in System Verilog using the open-source Verilint tool to check for lint errors. The next phase will be to integrate the design into the environment provided by AWS for prototyping on their EC2 F1 FPGA instance. This instance contains a Xilinx Ultrascale FPGA, DDR-1600 memory, and an Intel Broadcom processor for management functions.

There are many benefits to using the AWS F1 instance flow. The shell provided for integration of a custom design provides access to DDR-1600 memory using the AXI4 bus with a 512-bit interface. The hardware development kit (HDK) provides free access to compilation, synthesis, and timing tools. Prototyping the design on an FPGA serves the dual purpose of both verifying the design through functional tests as well as estimating encryption/decryption performance in bytes/clock via running benchmarks.

Please contact us at azimuthtechusa@gmail.com if you need further info.