Hi everyone – hope you and your families are enjoying the summer! Here is a status update on our progress.
RTL development of the closely coupled version of the cryptographic hardware accelerator (HWA) has commenced on Amazon Web Services (AWS).
The RTL is being coded in System Verilog using the open-source Verilint tool to check for lint errors. The next phase will be to integrate the design into the environment provided by AWS for prototyping on their EC2 F1 FPGA instance. This instance contains a Xilinx Ultrascale FPGA, DDR-1600 memory, and an Intel Broadcom processor for management functions.
There are many benefits to using the AWS F1 instance flow. The shell provided for integration of a custom design provides access to DDR-1600 memory using the AXI4 bus with a 512-bit interface. The hardware development kit (HDK) provides free access to compilation, synthesis, and timing tools. Prototyping the design on an FPGA serves the dual purpose of both verifying the design through functional tests as well as estimating encryption/decryption performance in bytes/clock via running benchmarks.
Please contact us at azimuthtechusa@gmail.com if you need further info.
